mirror of
https://github.com/godotengine/godot-nir-static.git
synced 2025-12-31 13:48:20 +03:00
Update mesa to 23.1.9
This commit is contained in:
1
.gitignore
vendored
1
.gitignore
vendored
@@ -1,3 +1,4 @@
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.sconsign.dblite
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bin/
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godot-mesa/
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*.pyc
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2
.gitmodules
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2
.gitmodules
vendored
@@ -1,3 +1,3 @@
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[submodule "mesa"]
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path = mesa
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url = https://github.com/Mesa3D/mesa
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url = https://gitlab.freedesktop.org/mesa/mesa
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@@ -322,6 +322,7 @@ else:
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]
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)
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env.Append(CFLAGS=["-std=c11"])
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env.Append(CXXFLAGS=["-fno-exceptions"])
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if env.get("use_llvm", False):
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extra_defines += [
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@@ -718,14 +718,15 @@ index 245c5140f9..d6c9d06c30 100644
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}
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static const struct dxil_value *
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@@ -5079,6 +5083,11 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
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@@ -5079,6 +5083,12 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_exclusive_scan:
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return emit_reduce(ctx, intr);
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+ case nir_intrinsic_load_constant_non_opt:
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+ case nir_intrinsic_load_constant_non_opt: {
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+ const struct dxil_value* value = get_src(ctx, &intr->src[0], 0, nir_type_uint);
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+ store_dest_value(ctx, &intr->dest, 0, value);
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+ return true;
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+ }
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+
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case nir_intrinsic_load_num_workgroups:
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case nir_intrinsic_load_workgroup_size:
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@@ -1,18 +0,0 @@
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diff --git a/godot-mesa/src/microsoft/compiler/nir_to_dxil.c b/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
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index d6c9d06..1e8e9ea 100644
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--- a/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
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+++ b/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
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@@ -5083,11 +5083,11 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_exclusive_scan:
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return emit_reduce(ctx, intr);
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- case nir_intrinsic_load_constant_non_opt:
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+ case nir_intrinsic_load_constant_non_opt: {
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const struct dxil_value* value = get_src(ctx, &intr->src[0], 0, nir_type_uint);
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store_dest_value(ctx, &intr->dest, 0, value);
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return true;
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-
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+ }
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case nir_intrinsic_load_num_workgroups:
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case nir_intrinsic_load_workgroup_size:
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default:
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@@ -23,8 +23,13 @@ def generate(env):
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if not env["use_mingw"] and msvc.exists(env):
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if env["arch"] == "x86_64":
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env["TARGET_ARCH"] = "amd64"
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elif env["arch"] == "arm64":
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env["TARGET_ARCH"] = "arm64"
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elif env["arch"] == "arm32":
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env["TARGET_ARCH"] = "arm"
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elif env["arch"] == "x86_32":
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env["TARGET_ARCH"] = "x86"
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env["is_msvc"] = True
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# MSVC, linker, and archiver.
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@@ -63,7 +68,15 @@ def generate(env):
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else:
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env["use_mingw"] = True
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# Cross-compilation using MinGW
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prefix = "i686" if env["arch"] == "x86_32" else env["arch"]
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if env["arch"] == "x86_64":
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prefix = "x86_64"
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elif env["arch"] == "arm64":
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prefix = "aarch64"
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elif env["arch"] == "arm32":
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prefix = "armv7"
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elif env["arch"] == "x86_32":
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prefix = "i686"
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if env["use_llvm"]:
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env["CXX"] = prefix + "-w64-mingw32-clang"
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env["CC"] = prefix + "-w64-mingw32-clang++"
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2
mesa
2
mesa
Submodule mesa updated: 9085c9d43e...52ab5584b8
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