Update mesa to 23.1.9

This commit is contained in:
bruvzg
2024-01-30 19:13:01 +02:00
parent f2e0daf5eb
commit 0985547d67
9 changed files with 21 additions and 23 deletions

1
.gitignore vendored
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@@ -1,3 +1,4 @@
.sconsign.dblite
bin/
godot-mesa/
*.pyc

2
.gitmodules vendored
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@@ -1,3 +1,3 @@
[submodule "mesa"]
path = mesa
url = https://github.com/Mesa3D/mesa
url = https://gitlab.freedesktop.org/mesa/mesa

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@@ -322,6 +322,7 @@ else:
]
)
env.Append(CFLAGS=["-std=c11"])
env.Append(CXXFLAGS=["-fno-exceptions"])
if env.get("use_llvm", False):
extra_defines += [

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@@ -718,14 +718,15 @@ index 245c5140f9..d6c9d06c30 100644
}
static const struct dxil_value *
@@ -5079,6 +5083,11 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
@@ -5079,6 +5083,12 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_exclusive_scan:
return emit_reduce(ctx, intr);
+ case nir_intrinsic_load_constant_non_opt:
+ case nir_intrinsic_load_constant_non_opt: {
+ const struct dxil_value* value = get_src(ctx, &intr->src[0], 0, nir_type_uint);
+ store_dest_value(ctx, &intr->dest, 0, value);
+ return true;
+ }
+
case nir_intrinsic_load_num_workgroups:
case nir_intrinsic_load_workgroup_size:

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@@ -1,18 +0,0 @@
diff --git a/godot-mesa/src/microsoft/compiler/nir_to_dxil.c b/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
index d6c9d06..1e8e9ea 100644
--- a/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
+++ b/godot-mesa/src/microsoft/compiler/nir_to_dxil.c
@@ -5083,11 +5083,11 @@ emit_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_exclusive_scan:
return emit_reduce(ctx, intr);
- case nir_intrinsic_load_constant_non_opt:
+ case nir_intrinsic_load_constant_non_opt: {
const struct dxil_value* value = get_src(ctx, &intr->src[0], 0, nir_type_uint);
store_dest_value(ctx, &intr->dest, 0, value);
return true;
-
+ }
case nir_intrinsic_load_num_workgroups:
case nir_intrinsic_load_workgroup_size:
default:

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@@ -23,8 +23,13 @@ def generate(env):
if not env["use_mingw"] and msvc.exists(env):
if env["arch"] == "x86_64":
env["TARGET_ARCH"] = "amd64"
elif env["arch"] == "arm64":
env["TARGET_ARCH"] = "arm64"
elif env["arch"] == "arm32":
env["TARGET_ARCH"] = "arm"
elif env["arch"] == "x86_32":
env["TARGET_ARCH"] = "x86"
env["is_msvc"] = True
# MSVC, linker, and archiver.
@@ -63,7 +68,15 @@ def generate(env):
else:
env["use_mingw"] = True
# Cross-compilation using MinGW
prefix = "i686" if env["arch"] == "x86_32" else env["arch"]
if env["arch"] == "x86_64":
prefix = "x86_64"
elif env["arch"] == "arm64":
prefix = "aarch64"
elif env["arch"] == "arm32":
prefix = "armv7"
elif env["arch"] == "x86_32":
prefix = "i686"
if env["use_llvm"]:
env["CXX"] = prefix + "-w64-mingw32-clang"
env["CC"] = prefix + "-w64-mingw32-clang++"

2
mesa

Submodule mesa updated: 9085c9d43e...52ab5584b8