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Vulkan: Remove BarrierType

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This was only used for one ASSERT, which is changed to use a correlated
variable.

Bug: angleproject:4959
Change-Id: I0eccd2c06c52fcfbff4c533e661735bf1213125d
Reviewed-on: https://chromium-review.googlesource.com/c/angle/angle/+/2371222
Commit-Queue: Shahbaz Youssefi <syoussefi@chromium.org>
Reviewed-by: Jamie Madill <jmadill@chromium.org>
This commit is contained in:
Shahbaz Youssefi
2020-08-23 00:39:28 -04:00
committed by Commit Bot
parent 6b175c5c40
commit 78304b470f
1 changed files with 6 additions and 31 deletions
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37
src/libANGLE/renderer/vulkan/vk_helpers.cpp
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@@ -65,12 +65,6 @@ constexpr angle::PackedEnumMap<PipelineStage, VkPipelineStageFlagBits> kPipeline
constexpr size_t kDefaultPoolAllocatorPageSize = 16 * 1024;
enum BarrierType
{
ReadOnly,
Write
};
struct ImageMemoryBarrierData
{
char name[40];
@@ -88,8 +82,6 @@ struct ImageMemoryBarrierData
// Access mask when transitioning out from this layout. Note that source access mask never
// needs a READ bit, as WAR hazards don't need memory barriers (just execution barriers).
VkAccessFlags srcAccessMask;
// Read or write.
BarrierType type;
// CommandBufferHelper tracks an array of PipelineBarriers. This indicates which array element
// this should be merged into. Right now we track individual barrier for every PipelineStage. If
// layout has a single stage mask bit, we use that stage as index. If layout has multiple stage
@@ -114,7 +106,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
0,
// Transition from: there's no data in the image to care about.
0,
BarrierType::ReadOnly,
PipelineStage::InvalidEnum,
},
},
@@ -129,7 +120,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
0,
// Transition from: all writes must finish before barrier.
VK_ACCESS_MEMORY_WRITE_BIT,
BarrierType::ReadOnly,
PipelineStage::InvalidEnum,
},
},
@@ -144,7 +134,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
// In case of multiple destination stages, We barrier the earliest stage
PipelineStage::TopOfPipe,
},
@@ -160,7 +149,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
// In case of multiple destination stages, We barrier the earliest stage
PipelineStage::TopOfPipe,
},
@@ -176,7 +164,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_TRANSFER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::Transfer,
},
},
@@ -191,7 +178,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_TRANSFER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_TRANSFER_WRITE_BIT,
BarrierType::Write,
PipelineStage::Transfer,
},
},
@@ -206,7 +192,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::VertexShader,
},
},
@@ -221,7 +206,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
PipelineStage::VertexShader,
},
},
@@ -236,7 +220,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::GeometryShader,
},
},
@@ -251,7 +234,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
PipelineStage::GeometryShader,
},
},
@@ -266,7 +248,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::FragmentShader,
},
},
@@ -281,7 +262,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
PipelineStage::FragmentShader,
},
},
@@ -296,7 +276,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::ComputeShader,
},
},
@@ -311,7 +290,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
PipelineStage::ComputeShader,
},
},
@@ -326,7 +304,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
// In case of multiple destination stages, We barrier the earliest stage
PipelineStage::VertexShader,
},
@@ -342,7 +319,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_SHADER_WRITE_BIT,
BarrierType::Write,
// In case of multiple destination stages, We barrier the earliest stage
PipelineStage::VertexShader,
},
@@ -358,7 +334,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT,
BarrierType::Write,
PipelineStage::ColorAttachmentOutput,
},
},
@@ -369,11 +344,10 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL,
kAllShadersPipelineStageFlags | VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT,
kAllShadersPipelineStageFlags | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT,
// Transition to: all reads and writes must happen after barrier.
// Transition to: all reads must happen after barrier.
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT,
// Transition from: all writes must finish before barrier.
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::EarlyFragmentTest,
},
},
@@ -388,7 +362,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
// Transition from: all writes must finish before barrier.
VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
BarrierType::Write,
PipelineStage::EarlyFragmentTest,
},
},
@@ -408,7 +381,6 @@ constexpr angle::PackedEnumMap<ImageLayout, ImageMemoryBarrierData> kImageMemory
0,
// Transition from: RAR and WAR don't need memory barrier.
0,
BarrierType::ReadOnly,
PipelineStage::BottomOfPipe,
},
},
@@ -3488,7 +3460,10 @@ bool ImageHelper::updateLayoutAndBarrier(VkImageAspectFlags aspectMask,
if (newLayout == mCurrentLayout)
{
const ImageMemoryBarrierData &layoutData = kImageMemoryBarrierData[mCurrentLayout];
ASSERT(layoutData.type == BarrierType::Write);
// srcAccessMask == 0 is only possible for read-only layouts. RAR is not a hazard and
// doesn't require a barrier, especially as the image layout hasn't changed. The following
// asserts that such a barrier is not attempted.
ASSERT(layoutData.srcAccessMask != 0);
// No layout change, only memory barrier is required
barrier->mergeMemoryBarrier(layoutData.srcStageMask, layoutData.dstStageMask,
layoutData.srcAccessMask, layoutData.dstAccessMask);